The present invention relates to a semiconductor memory device and a method of manufacturing the same.
Among nonvolatile semiconductor memory devices, a flash memory, for example, has a structure in which gate oxide films are formed on a semiconductor substrate and polysilicon films are formed on the gate oxide films as floating gate electrodes.
On the semiconductor substrate, there are formed element-isolating trenches to isolate the floating gate electrodes of memory cells. Element-isolating insulating films are buried in the trenches and are etched so that the top surface thereof is higher than the surface of the semiconductor substrate but is lower than the top surface of the floating gate electrodes.
An insulating film for covering the floating gate electrodes and the element-isolating insulating films is formed and a polysilicon film for forming control gate electrodes is further formed on the insulating film.
Since the top surface of the element-isolating insulating films is lower than the top surface of the floating gate electrodes, the insulating film is of concavo-convex shape according to the surface shapes of the underlying floating gate electrodes and the element-isolating insulating films.
In addition, the bottom surface of the control gate electrodes is also of concavo-convex shape according to the surface shape of the underlying insulating film.
By applying such a structure as described above, it is possible to secure surface areas, with respect to the insulating film formed between the floating gate electrodes and the control gate electrodes, also on the lateral sides of each floating gate electrode, thereby making it possible to increase the coupling capacitance and coupling ratio.
The chip of the semiconductor memory device has a memory cell array portion and a peripheral portion. Since the etching of the above-described element-isolating insulating films is carried out in order to increase the coupling capacitance or coupling ratio, only an area within the memory cell array portion is etched. Thus, no etching is performed on the peripheral portion for which the coupling capacitance need not be increased. In other words, the peripheral portion is masked when etching the element-isolating insulating films.
However, if element-isolating insulating films are etched under the same conditions (time) when manufacturing products wherein the occupation ratios of memory cell array portions in chips differ, the amount of element-isolating insulating films to be etched away also differs product by product since the opening ratio of an etching mask differs product by product.
Consequently, there arises a difference in the height of the element-isolating insulating films from the surface of the semiconductor substrate. Since the coupling ratio varies if this height changes, there arises a difference in program voltage.
Accordingly, a variation may arise in the program voltage of products wherein the occupation ratios of memory cell array portions differ, thereby degrading product reliability.